1. Field of the Invention
The present invention relates to a decoding apparatus and a decoding method for decoding turbo-coded data, and a data receiving apparatus and a data receiving method for employing the turbo decoding.
2. Description of Related Art
Recently, there is proposed an encoding method employing Turbo Codes as error correcting codes which can substantially realize the Shannon limit. The turbo codes have been studied and improved as codes with high performance and high reliability for use in various fields including mobile communication and digital broadcasting. The turbo codes are referred to also as Parallel Concatenated Convolution Codes (PCCC).
A turbo encoder is configured by concatenating a plurality of encoders in parallel. Specifically, for example, two convolutional encoders and an interleaver are concatenated in parallel. In decoding turbo-coded data, a plurality of decoders are used, and decoding processing is performed repeatedly using the reliability of resulting decoded data. Thus, exchanging information therebetween, the decoders can obtain ultimate decoded data. In performing the decoding processing, the soft decision decoding such as the MAP (Maximum a-posteriori Probability) algorithm.
Next, a turbo encoder for performing turbo encoding and a turbo decoder for performing turbo decoding will be explained hereinafter with reference to drawings.
FIG. 1 shows a block diagram of the turbo encoder for performing above-described turbo encoding. As shown, input data from an input terminal 101 is sent to a parallel-to-serial converter 102, and to a convolutional encoder 103. The input data is sent also to a convolutional encoder 105 via an interleaver 104.
The convolutional encoder 103 performs convolutional computing for the input data, and sends the resulting data to the parallel-to-serial converter 102 as parity bit Da. The convolutional encoder 103 consists of, for example, an adder 111, two delay elements such as D flip-flops (DFFs) 112, 113, and an adder 114. The interleaver 104 changes the order of bits constituting the input data to rearrange the bits, and sends the resulting interleaved data to the convolutional encoder 105. The convolutional encoder 105, which has the same configuration as that of the convolutional encoder 103, performs convolutional computing for the interleaved input data, and sends the resulting data to the parallel-to-serial converter 102 as parity bit Db. The encoding processing is performed every block consisting of bits of a predetermined number, which becomes the unit of the encoding processing, and this block is referred to also as a code block.
The parallel-to-serial converter 102 converts systematic bit Ds, which is the original input data from the input terminal 101, the parity bit Da from the convolutional encoder 103, the parity bit Db from the convolutional encoder 105 to serial data, and outputs the resulting data from an output terminal 106. The output data undergoes predetermined modulating processing for communication to be transmitted.
FIG. 2 shows a block diagram of the turbo decoder which corresponds to above-described turbo encoder. An input terminal 121 receives a signal, which is encoded by above-described turbo encoder, and is modulated to be transmitted, and then is received by the turbo decoder and demodulated. The received signal is sent to a normalizing circuit 122 adapted for adjusting the signal level of a signal sent thereto appropriately, and then is sent to a serial-to-parallel converter 123.
The serial-to-parallel converter 123, which corresponds to the parallel-to-serial converter 102 shown in FIG. 1, divides the received signal into the systematic bit Ds, parity bit Da, and parity bit Db. The separated systematic bit Ds is sent to a soft output decoding unit 124 and to an interleaver 125. The separated parity bit Da is sent to the soft output decoding unit 124. The separated parity bit Db is sent to the soft output decoding unit 126. An output from the soft output decoding unit 124 is sent to the soft output decoding unit 126 via an interleaver 127, and an output from the soft output decoding unit 126 is fed-back to the soft output decoding unit 124 via a deinterleaver 128. And, this decoding processing is to be performed repeatedly by the code block unit, that is, repetitively decoding (turbo decoding) processing is to be performed. Ultimate decoded data from the soft output decoding unit 126 is converted to binary data by a hard deciding circuit 129, and is deinterleaved by a deinterleaver 130, and the resulting data is sent to an output terminal 131 to be sent therefrom.
The soft output decoding unit 124 consists of a MAP (Maximum a-posteriori Probability) algorithm circuit 134 and an adder 135. The MAP algorithm circuit 134 receives the systematic bit Ds and parity bit Da from the serial-to-parallel converter 123, and an output from the deinterleaver 128. An output from the MAP algorithm circuit 134 is sent to the adder 135. The adder 135 subtracts the systematic bit Ds and output of the deinterleaver 128 from the output of the MAP algorithm circuit 134. An output from the adder 135 is sent to the interleaver 127.
The soft output decoding unit 126 consists of a MAP algorithm circuit 136 and an adder 137. The MAP algorithm circuit 136 receives an output from the interleaver 125, the parity bit Db from the serial-to-parallel converter 123, and an output from the interleaver 127. An output from the MAP algorithm circuit 136 is sent to a hard deciding circuit 129 and the adder 137. The adder 137 subtracts the output of the interleaver 125 and output of the interleaver 127 from the output of the MAP algorithm circuit 136. An output from the adder 137 is sent to the deinterleaver 128.
A timing controlling circuit 133 controls the operation timing of the serial-to-parallel converter 123, MAP algorithm circuits 134 and 136, interleavers 125 and 127, and deinterleavers 128 and 130 of the turbo decoder, respectively.
In the turbo decoder shown in FIG. 2, the decoding processing is to be repeated several times or scores of times. Before performing the repetitive decoding processing, the interleaver 125 stores the systematic bit Ds of the input signal in advance. Also, the deinterleaver 128 is caused to be initialized with an initial value (zero) in advance.
Next, one of the repetitive decoding processing of the turbo decoding will be explained briefly. Firstly, at the first half of the processing, the MAP algorithm of the MAP algorithm circuit 134 is operated. In performing the processing of the MAP algorithm, the systematic bit Ds, parity bit Da, and output from the deinterleaver 128 are used. An output generated by performing the processing of the MAP algorithm is sent to the interleaver 127 via the adder 135, and is stored in the interleaver 127. At the first time of the repetitive decoding processing, since the interleaver 127 has stored therein no information, the initial value (zero) is used. At the latter half of the processing, the MAP algorithm of the MAP algorithm circuit 136 is operated. In performing the processing of the MAP algorithm, interleaved systematic bit Ds from the interleaver 125, the parity bit Db from the serial-to-parallel converter 123, and the output from the interleaver 127 are used. An output generated by performing the processing of the MAP algorithm is sent to the deinterleaver 128 via the adder 137, and is stored in the deinterleaver 128. The output generated by performing the processing of the MAP algorithm is hard-decided by the hard deciding circuit 129, and the resulting output (sign bits) is sent to the deinterleaver 130 to be stored therein.
This is the brief explanation of one of the repetitive decoding processing of the turbo decoding. After performing this processing several times which is determined in advance, the finally decoded data stored in the deinterleaver 130 which is obtained by performing the processing of the MAP algorithm of the MAP algorithm circuit 136 is sent to the output terminal 131 to be output therefrom as ultimate decoded data.
Next, one example of a data transmitting/receiving apparatus employing above-described turbo encoding technique and turbo decoding technique will be explained with reference to FIG. 3.
FIG. 3 shows a block diagram of the data transmitting/receiving apparatus. A signal received by an antenna 1 is sent to a low noise amplifier 3 via a shared device 2 for, sharing the antenna 1 at the time of transmitting/receiving a signal. The received signal is amplified by the low noise amplifier 3, and is converted to a baseband signal by a reception RF (Radio Frequency) unit 4, and then is demodulated by a demodulating unit 5 by undergoing baseband signal processing. The demodulated signal is turbo-decoded by a turbo decoder 6 corresponding to the turbo decoder in FIG. 2, and is sent to a terminal interface (I/F) unit 7. The terminal I/F unit 7 sends the received packet data to a data terminal 8. The resulting decoded data from the turbo decoder 6 is sent to a CRC (Cyclic Redundancy Check) recalculating unit 9 to undergo the CRC recalculation. Then, it is judged whether or not check bits included in the decoded data accord with the calculated result, that is whether or not error is generated, and the judgement result is sent to the terminal I/F unit 7 and to a packet flow retransmission controlling unit 10.
Data to be transmitted from the data terminal 8 is sent to a turbo encoding and frame forming unit 11 via the terminal I/F unit 7 and packet flow retransmission controlling unit 10 to undergo the turbo encoding processing described with reference to FIG. 1 and frame forming processing. The encoded data from the turbo encoding and frame forming unit 11 is modulated by a modulating unit 12, and is converted to an RF signal by a transmission RF unit 13, and is amplified by a power amplifier 14, and then is sent to the antenna 1 via the shared device 2.
In case it is determined that the error detection result from the CRC recalculating unit 9 shows that there exists no bit error, the terminal I/F unit 7 discards the received packet data, and the packet flow retransmission controlling unit 10 sends a signal requesting retransmission of packet data to the turbo encoding and frame forming unit 11 of the transmitting unit.
Above-described conventional data transmitting/receiving apparatus performs the error detection by the use of error detecting codes. On the other hand, there remains a possibility that the error detection using the error detection codes cannot be performed correctly under a certain probability. In this case, there occurs a problem that incorrect packet data is undesirably sent to the data terminal 8. Also, in case there exist incorrect bits, even though one bit, all the packet is to be retransmitted, which lowers the data transmission efficiency.